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NBSG16 2.5V/3.3V SiGe Differential Receiver/Driver with RSECL* Outputs
*Reduced Swing ECL
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The NBSG16 is a differential receiver/driver targeted for high frequency applications. The device is functionally equivalent to the EP16 and LVEP16 devices with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used as a reference voltage for single-ended NECL or PECL inputs and the VMM pin is used as a reference voltage for LVCMOS inputs. For all single-ended input conditions, the unused complementary differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open.
MARKING DIAGRAM*
SG 16 LYW
FCBGA-16 BA SUFFIX CASE 489
QFN-16 MN SUFFIX CASE 485G
SG16 ALYW
* * * * * * *
Maximum Input Clock Frequency > 12 GHz Typical Maximum Input Data Rate > 12 Gb/s Typical 120 ps Typical Propagation Delay 40 ps Typical Rise and Fall Times RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 W Internal Input Termination Resistors
A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For further details, refer to Application Note AND8002/D
ORDERING INFORMATION
Device NBSG16BA NBSG16BAR2 Package 4x4 mm FCBGA-16 4x4 mm FCBGA-16 3x3 mm QFN-16 3x3 mm QFN-16 Shipping 100 Units/Tray 500/Tape & Reel
* * Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices * VBB and VMM Reference Voltage Output
NBSG16MN NBSG16MNR2
123 Units/Rail 3000/Tape & Reel
Board NBSG16BAEVB
Description NBSG16BA Evaluation Board
(c) Semiconductor Components Industries, LLC, 2003
1
May, 2003 - Rev. 12
Publication Order Number: NBSG16/D
NBSG16
1 A
VEE
2
NC
3
NC
4
VEE
VEE VBB 16 VTD 15
VMM VEE 14 13 Exposed Pad (EP)
1 2 NBSG16 3 4
12 11 10 9
VCC Q Q VCC
B
D
VTD
VCC
Q
D D VTD
C
D
VTD
VCC
Q
D
VEE
VBB
VMM
VEE
5 VEE
6 NC
7 NC
8 VEE
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin BGA C2 C1 QFN 1 2 Name VTD D I/O ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input RSECL Output RSECL Output Description Internal 50 W Termination Pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
B1
3
D
Noninverted differential input. Internal 75 kW to VEE.
B2 A1,D1,A4, D4 A2,A3 B3,C3 B4 C4 D3 D2 N/A
4 5,8,13,16 6,7 9,12 10 11 14 15 -
VTD VEE NC VCC Q Q VMM VBB EP
Internal 50 W Termination Pin. See Table 2. Negative Supply Voltage No Connect Positive Supply Voltage Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V LVCMOS Reference Voltage Output. (VCC - VEE)/2 ECL Reference Voltage Output Exposed Pad. (Note 2)
1. The NC pins are electrically connected to the die and MUST be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation.
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NBSG16
VCC
VTD 50 W D D 50 W VTD 75 kW
36.5 KW
VMM
Q Q 75 kW VBB
VEE
Figure 3. Logic Diagram
Table 2. Interfacing Options
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL CONNECTIONS Connect VTD and VTD to VCC Connect VTD and VTD together Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. VMM should be connected to the unused complementary differential input.
LVCMOS
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Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor (D, D) Internal Input Pullup Resistor (D) ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Human Body Model Machine Model FCBGA-16 QFN-16 Oxygen Index: 28 to 34 Value 75 kW 36.5 kW > 2 kV > 100 V Level 3 Level 1 UL 94 V-0 @ 0.125 in 167
Table 4. MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI VINPP Iout IBB IMM TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Output Current VBB Sink/Source VMM Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 1S2P (Note 3) 2S2P (Note 4) < 15 sec. 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN |D - D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC - VEE w VCC - VEE < Continuous Surge 2.8 V 2.8 V VI VCC VI VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 |VCC - VEE| 25 50 1 1 -40 to +85 -65 to +150 108 86 41.6 35.2 5 4.0 225 Units V V V V V V mA mA mA mA C C C/W C/W C/W C/W C/W C/W C
qJC Tsol
Thermal Resistance (Junction-to-Case) Wave Solder
2. Maximum Ratings are those values beyond which device damage may occur. 3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5)
-40 C Symbol IEE VOH VOUTPP VIH VIL VBB VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 6) Output Voltage Amplitude Input HIGH Voltage (Single-Ended) (Note 7) Input LOW Voltage (Single-Ended) (Note 7) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 8) (Differential Configuration) CMOS Output Voltage Reference VCC/2 Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 17 1450 350 VTHR + 75 mV VEE 1080 1.2 Typ 23 1530 410 VCC 1.0* VCC 1.4* 1140 Max 29 1575 525 VCC VTHR 75 mV 1200 2.5 Min 17 1525 350 VTHR + 75 mV VEE 1080 1.2 25C Typ 23 1565 410 VCC 1.0* VCC 1.4* 1140 Max 29 1600 525 VCC VTHR 75 mV 1200 2.5 Min 17 1550 350 VTHR + 75 mV VEE 1080 1.2 85C Typ 23 1590 410 VCC 1.0* VCC 1.4* 1140 Max 29 1625 525 VCC VTHR 75 mV 1200 2.5 Unit mA mV mV V V mV V
VMM RTIN IIH IIL
1100 45
1250 50 30 25
1400 55 100 50
1100 45
1250 50 30 25
1400 55 100 50
1100 45
1250 50 30 25
1400 55 100 50
mV W mA mA
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 6. All loading with 50 W to VCC-2.0 volts. 7. VTHR is the voltage applied to the complementary input, typically VBB or VMM. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes.
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 9)
-40 C Symbol IEE VOH VOUTPP VIH VIL VBB VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 10) Output Voltage Amplitude Input HIGH Voltage (Single-Ended) (Note 11) Input LOW Voltage (Single-Ended) (Note 11) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 12) (Differential Configuration) CMOS Output Voltage Reference VCC/2 Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 17 2250 350 VTHR + 75 mV VEE 1880 1.2 Typ 23 2330 410 VCC 1.0* VCC 1.4* 1940 Max 29 2375 525 VCC VTHR 75 mV 2000 3.3 Min 17 2325 350 VTHR + 75 mV VEE 1880 1.2 25C Typ 23 2365 410 VCC 1.0* VCC 1.4* 1940 Max 29 2400 525 VCC VTHR 75 mV 2000 3.3 Min 17 2350 350 VTHR + 75 mV VEE 1880 1.2 85C Typ 23 2390 410 VCC 1.0* VCC 1.4* 1940 Max 29 2425 525 VCC VTHR 75 mV 2000 3.3 Unit mA mV mV V V mV V
VMM RTIN IIH IIL
1500 45
1650 50 30 25
1800 55 100 50
1500 45
1650 50 30 25
1800 55 100 50
1500 45
1650 50 30 25
1800 55 100 50
mV W mA mA
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. 10. All loading with 50 W to VCC - 2.0 V. 11. VTHR is the voltage applied to the complementary input, typically VBB or VMM. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes.
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NBSG16
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 13) -40 C Symbol IEE VOH VOUTPP VIH VIL VBB VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 14) Output Voltage Amplitude Input HIGH Voltage (Single-Ended) (Note 15) Input LOW Voltage (Single-Ended) (Note 15) NECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 16) (Differential Configuration) CMOS Output Voltage Reference (Note 17) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 17 -1050 350 VTHR + 75 mV VEE -1420 Typ 23 -970 410 VCC 1.0* VCC 1.4* -1360 Max 29 -925 525 VCC VTHR 75 mV -1300 0.0 Min 17 -975 350 VTHR + 75 mV VEE -1420 25C Typ 23 -935 410 VCC 1.0* VCC 1.4* -1360 Max 29 -900 525 VCC VTHR 75 mV -1300 0.0 Min 17 -950 350 VTHR + 75 mV VEE -1420 85C Typ 23 -910 410 VCC 1.0* VCC 1.4* -1360 Max 29 -875 525 VCC VTHR 75 mV -1300 0.0 Unit mA mV mV V V mV V
VEE+1.2
VEE+1.2
VEE+1.2
VMM RTIN IIH IIL
VMMT -150 45
VMMT 50 30 25
VMMT + 150 55 100 50
VMMT -150 45
VMMT 50 30 25
VMMT + 150 55 100 50
VMMT -150 45
VMMT 50 30 25
VMMT + 150 55 100 50
mV W mA mA
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 13. Input and output parameters vary 1:1 with VCC. 14. All loading with 50 W to VCC -2.0 volts. 15. VTHR is the voltage applied to the complementary input, typically VBB or VMM. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 17. VMM typical = |VCC - VEE|/2 + VEE = VMMT *Typicals used for testing purposes.
Table 8. AC CHARACTERISTICS for FCBGA-16
VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 C Symbol fmax tPLH, tPHL tSKEW tJITTER Characteristic Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 18) Propagation Delay to Output Differential Duty Cycle Skew (Note 19) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 20) Output Rise/Fall Times @ 1 GHz (20% - 80%) Q, Q 75 30 45 0.2 TBD 2600 75 75 20 40 1 0.2 TBD 2600 65 75 20 40 1 0.2 TBD 2600 65 mV ps 1 Min 10.7 90 Typ 12 110 3 130 15 Max Min 10.7 100 25C Typ 12 120 3 140 15 Max Min 10.7 105 85C Typ 12 125 3 145 15 Max Unit GHz ps ps ps
18. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 19. See Figure 6. tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform. 20. VINPP(max) cannot exceed VCC - VEE
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Table 9. AC CHARACTERISTICS for QFN-16
VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 C Symbol fmax tPLH, tPHL tSKEW tJITTER Characteristic Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 21) Propagation Delay to Output Differential Duty Cycle Skew (Note 22) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 23) Output Rise/Fall Times @ 1 GHz (20% - 80%) Q, Q 75 20 30 0.2 TBD 2600 50 75 20 30 2 0.2 TBD 2600 50 75 20 30 2 0.2 TBD 2600 50 mV ps 2 Min 10.7 90 Typ 12 110 3 130 15 Max Min 10.7 100 25C Typ 12 120 3 140 15 Max Min 10.7 95 85C Typ 12 125 3 145 15 Max Unit GHz ps ps ps
21. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 22. See Figure 6. tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform. 23. VINPP(max) cannot exceed VCC - VEE
700 9.5 OUTPUT VOLTAGE AMPLITUDE (mV) 600 500 OUTPUT AMP 400 300 200 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 INPUT FREQUENCY (GHz) Q Q 8.5 JITTEROUT ps (RMS) 7.5 6.5 5.5 4.5 3.5 2.5 1.5 RMS JITTER 0.5 -0.5
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical)
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NBSG16
X = 17ps/Div
Y = 70 mV/Div
Figure 5. 10.709 Gb/s Diagram (3.0 V, 255C)
D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 6. AC Reference Measurement
Q Driver Device Q 50 W 50 W
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
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PACKAGE DIMENSIONS
FCBGA-16 BA SUFFIX PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
-XD M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC
-YK E
M 0.20
3X FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D
e
4
3
2
1
3
16 X
b 0.15 0.08
M M
S VIEW M-M
ZXY Z
5 0.15 Z A A2 -Z-
A1
16 X
4 DETAIL K
0.10 Z
ROTATED 90 _ CLOCKWISE
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PACKAGE DIMENSIONS
16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE O
-XA M -YNOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A B C D E F G H J K L M N P R SEATING PLANE MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031
B N 0.25 (0.010) T 0.25 (0.010) T J R 0.08 (0.003) T E H G
5 8
C K -T-
L
4
9
F
1 12
16
13
P
D
NOTE 3 M
0.10 (0.004)
TXY
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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